1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, it relates to a technique for ensuring electrical connection between a contact plug and an impurity layer even on the occurrence of misalignment of a contact hole.
2. Description of the Background Art
FIG. 31 is a perspective view illustrating a semiconductor device or semiconductor memory device 901 according to a first background art. The semiconductor device 901 is a semiconductor memory device including a plurality of transistors each having a so-called MONOS (metal-oxide-nitride-oxide-semiconductor) structure. This type of semiconductor memory device is disclosed in U.S. Pat. No. 5,768,192, for example.
The semiconductor device 901 has a plurality of N-type impurity layers 911 forming stripes in a main surface 910S of a P-type semiconductor substrate 910. An ONO film 921 serving as a gate insulating film is arranged on the main surface 910S. The ONO film 921 may be alternatively referred to as gate insulating film 921. The ONO film 921 is of a stacked structure including silicon oxide/silicon nitride/silicon oxide. To avoid complication, each layer for forming the ONO film 921 is not shown. A plurality of gate electrodes 930 are arranged on the ONO film 921. The gate electrodes 930 form stripes orthogonal to the N-type impurity layers 911. Further, an interlayer insulating film 922 is provided to cover the gate electrodes 930.
Each memory element or each unit cell of the semiconductor device 901 has a transistor structure defined by one pair of impurity layer 911 and one gate electrode 930. In each unit cell, carriers are transferred to and from the impurity layer 911 and the gate electrode 930, introducing fixed charge in the ONO film 921. The fixed charge thus introduced causes variation in threshold value of a transistor, thereby allowing storage and holding of information (data). The gate electrode 930 and the impurity layer 911 serve as a word line and a bit line, respectively. By setting voltage value to be applied to the plurality of gate electrodes 930 and to the plurality of impurity layers 911, unit cell is selected (bit is selected). The gate electrode 930 and the impurity layer 911 may be alternatively referred to as word line 930 and bit line 911, respectively.
It is generally desired to perform writing and reading of information at high speed in the semiconductor memory device. By selectively applying voltage to the word line 930 and the bit line 911, information is written in and read out in the semiconductor device 901. For speedup in writing and reading, it is required to transmit signals at high speed over the word line 930 and the bit line 911. As an effective measure for this, electrical resistance in the word line 930 and the bit line 911 should be reduced. Particularly, the bit line 911 includes an impurity layer in the semiconductor substrate 910 and therefore, the bit line 911 has relatively high resistance. In view of this, a semiconductor device according to a second background art will be introduced next having the bit line 911 lower in resistance than the one in the semiconductor device 901.
FIGS. 32 and 33 are a perspective view and a plan view (layout), respectively, illustrating a semiconductor device or semiconductor memory device 901B according to the second background art. FIGS. 34 and 35 are sectional views taken along cutting lines 34—34 and 35—35 in FIG. 33, respectively. To avoid complication, some constituent elements are suitably omitted from FIGS. 31, 32 and 33. For example, a contact plug 923 is not shown in FIG. 32.
A plurality of low-resistance wires 940 and a plurality of contact plugs 923 are added to the above-described semiconductor device 901, to reach the structure of the semiconductor device 901B. More particularly, the low-resistance wires 940 includes metal such as aluminum (Al) lower in resistance than that of the impurity layer 911. The low-resistance wires 940 form stripes extending in the same direction as that of the impurity layers 911. Further, the low-resistance wires 940 are arranged directly above the impurity layers 911.
The interlayer insulating film 922 includes a plurality of contact holes 920H formed therein. The contact holes 920H are arranged directly on the respective ones of the plurality of impurity layers 911. The contact plug 923 is provided in each contact hole 920H. Electrical connection is thus established between the low-resistance wire 940 and impurity layer 911 facing each other through the contact plug 923.
The impurity layer 911 has connection to the low-resistance wire 940 lower in resistance than the impurity layer 911. Therefore, resistance in the impurity layer (bit line) 911 is effectively reduced, thereby allowing speedup in signal transmission over the bit line 911. As a result, according to the semiconductor device 901B, writing and reading can be performed at higher speed than the semiconductor device 901.
As described, in the semiconductor device 901B, each contact plug 923 is utilized for electrically connecting the corresponding impurity layer 911 and the low-resistance wire 940. When the contact hole 920H is not formed at its proper position bringing the contact plug 923 into contact with a region of the main surface 910S other than the N-type impurity layer 911, malfunction of the semiconductor device 901B may occur. More particularly, due to the foregoing misalignment of the contact hole 920H, a short circuit occurs through the contact plug 923 between the N-type impurity layer 911 and the P-type region of semiconductor substrate 910, resulting in malfunction of the unit cell (memory element) including such impurity layer 911.
The degree of the foregoing misalignment may be reduced by ensuring alignment margin for the impurity layer 911 and the contact hole 920H to a sufficient extent. However, increase in alignment margin leads to an extended layout area. Therefore, a demand for shrinkage of a semiconductor device cannot be met. Further, the word line 930 and the bit line 911 extend to a larger degree as the layout area increases, causing increase in resistance therein. As a result, high speed operations are less effectively realized.